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| ESMT Preliminary AD8258A Stereo/Mono Digital Audio Amplifier with Headphone Driver and SubWoofer Line-Out Features 16/18/20/24-bit input with I S, Left-alignment and Right-alignment data format PSNR & DR(A-weighting) Loudspeaker: 92dB (PSNR), 89dB (DR) @24V Headphone: 86dB (PSNR), 86dB (DR) Multiple sampling frequencies (Fs) 32kHz / 44.1kHz / 48kHz and 64kHz / 88.2kHz / 96kHz 128kHz/176.4kHz/192kHz System clock = 64x, 128x, 192x, 256x, 384x, 512x, 576x, 768x, 1024x Fs 64x~1024x Fs for 32kHz / 44.1kHz / 48kHz 64x~512x Fs for 64kHz / 88.2kHz / 96kHz 64x~256x Fs for 128kHz/176.4kHz/192kHz Supply voltage 12V~24V for loudspeaker driver 3.0~3.3V for others Loudspeaker output power for 24V 2x28W into 8@1% THD+N for stereo 2x35W into 8@10% THD+N for stereo 1x55W into 4@1% THD+N for mono 1x70W into 4@10% THD+N for mono Headphone power 40mW into 32@1kHz and 1% THD+N 80mW into 16@1kHz and 1% THD+N Sound processing including Bass (+18dB~-12dB, 3dB frequency is 250Hz), Treble (+18dB~-12dB, 3dB frequency is 7kHz), 5 bands parametric EQ, 2 Volume control (+24dB~-103dB, 1dB/step) and Dynamic range control Anti-pop design Over-temperature protection Under-voltage shutdown Short-circuit protection I2C control interface Subwoofer line-out support Applications CD and DVD TV audio Car audio Boom-box MP3 docking systems Portable / Handheld Powered speaker Wireless audio USB speaker Description This is a stereo/mono fully digital audio amplifier with output power which can drive 8/4load with up to 24 V voltage supply. Using I2C digital control interface, AD8258A provides sound processing includes Volume, Bass, Treble, EQ, Mixing and Dynamic Range Control (DRC). Protection circuits are provided to protect AD8258A damage while connection error. It is possible to compose of 2.1 channels with two pieces of AD8258A and 5.1 channels with four pieces. ORDERING INFORMATION Product Number AD8258A Package 10x10 64L E-LQFP Comments Pb-free Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2007 Revision: 0.1 1/37 ESMT Pin Assignment Preliminary AD8258A Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME N.C. N.C. N.C. N.C. PLL_Byp MCLK CLK_OUT DGND TV DVDD DEF FSEL I I O P I P I I Master clock input Clock output from PLL Digital Ground 1: hardware control, 0:I2C control Digital Power Default volume setting 0: 48kHz, 1:96kHz Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer TTL output buffer TYPE DESCRIPTION CHARACTERISTICS Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2007 Revision: 0.1 2/37 ESMT 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 FS192 N.C. N.C. N.C. N.C. N.C. SDATA0 SDATA1 MONO LRCIN BCLK PD Preliminary I 192k sampling rate selection AD8258A Schmitt trigger TTL input buffer I I I I I I O I I I O O Serial audio data input 0 Serial audio data input 1 MONO mode enable: high active Left/Right clock input (Fs) Bit clock input (64Fs) Power down, low active Error status Reset, low active I2C select address 0 I2C select address 1 Subwoofer output + / half-bridge output Subwoofer output - Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Open-drain output Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer TTL output buffer TTL output buffer ERROR RESET SA0 SA1 SUBA SUBB N.C. N.C. N.C. N.C. SCL SDA DGND DVDD PVDDR HPR VCM AGND AVDD HP_SPK HPL PVDDL N.C. N.C. I I/O P P P O O P P I O P I2C serial clock input I2C bi-directional serial data Digital Ground Digital Power Headphone Right channel supply Headphone R channel output Headphone Common-Mode voltage Analog ground Analog supply Selection between Headphone and Speaker 1: Headphone 0:Speaker Headphone L channel output Headphone Left channel supply Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2007 Revision: 0.1 3/37 |
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